A controller area network (CAN) bus, such as that compliant with the ISO 11898 standard, is used in several systems including industrial, automotive, robotic, and motor control systems to provide a serial communication physical layer. The robust CAN bus provides low power requirements, space savings and reduced resources. As shown in FIG. 1, a CAN node is comprised of three basic parts: a processor, a network controller, and a transceiver. The transceiver interfaces the single-ended CAN controller with the differential CAN bus. The bus, as shown in FIG. 2, includes multiple nodes that transmit messages on-demand by any node whenever the bus is free. The transceiver broadcasts data such that all nodes receive each message sent on the bus, including the node that sent it. The effect of broadcasting of data allows multiple nodes to utilize the data transmitted.
Texas Instruments, Inc. ® has introduced CAN transceiver models: SN65HVD230, SN65HVD231, and SN65HVD232, for use in applications employing the CAN serial communication physical layer compatible with the ISO 11898 Standard. As a CAN transceiver, as shown in FIG. 3a, each model provides differential transmit capability to the bus and differential receive capability to a CAN controller at speeds of up to 1 Mbps. Designed for operation in especially harsh environments, the CAN transceiver features cross-wire, over voltage and loss of ground protection from −4 V to +16 V, over-temperature protection as well as −2 V to 7 V common-mode range, and withstands transients of ±25 V.
FIG. 3b represents the timing diagrams of several signals including the signals found at driver node D, receiver node R, differential nodes, CANH and CANL, and voltage output differential Vod of CAN transceiver 10. As shown, when the driver input D is low, the differential output nodes, CANH and CANL, are high and low respectively. When the driver input D is high, however, transceiver 10 goes into a tri-state mode where the differential output nodes, CANH and CANL, are both tri-state.
In general, the input capacitance of the receiver comparator 14 is capacitively balanced without any added circuitry if the transistors that form the input differential pair within the receiver comparator 14 are made the same size. Conventionally, these transistors are made the same size. Driver 12, however, includes driver outputs that tend to be the source of capacitive imbalance on the receiver input pins.
To correct this capacitive imbalance, additional impedance balancing circuitry must be added to the differential nodes, CANH and CANL, in compliance with the ISO 11898 physical layer standard. Driver arbitration problems arise when one driver on the bus is trying to pull a bus line low while another driver is trying to the pull the same bus line high. The ISO 11898 physical layer standard avoids driver arbitration problems by requiring that only an active pull-up device may be connected to the CANH node and only an active pull-down device may be connected to the CANL node.
A known CAN transceiver compliant with ISO 11898 physical layer standard, as shown in FIG. 4, includes impedance matching circuitry formed using bipolar transistors, 36 and 42, and blocking Schottky diodes, 38 and 40 connected as shown. Differential node CANH1 uses a PNP (or PMOS) transistor 36 as an active device, while differential node CANL1 uses a NPN (or an NMOS) transistor 40 as an active device. A disadvantage of this design is that the upper PNP transistor 36 connected to node CANH1 must be substantially larger than the lower NPN transistor 42 connected to node CANL1 to meet output differential voltage requirements of the ISO11898 standard. Since upper PNP transistor 36 has more capacitance than the lower NPN transistor 42 and the driver outputs, 44 and 46, are indirectly connected in parallel to the receiver inputs, CANH1 and CANL1, through transistors, 36 and 42, capacitive imbalance still exists on the receiver inputs, CANH1 and CANL1. Conventionally, the CANH1 node will have a capacitance of 18 pF while the CANL1 node will have a capacitance of 7 pF, leaving a difference of 11 pF.
Furthermore, capacitive imbalance presents another problem in that it prevents the transceiver from passing a common mode rejection test which is conducted in an effort to make certain that the impedance matching circuitry guards the receiver against common-mode transients such as noise which causes the differential output nodes, CANH1 and CANL1, to be pulled higher than the power supply rail voltage VCC or lower than ground.
Given a common-mode rejection test implementation, as shown in FIG. 5a, if during the application of the input differential voltage to the differential output nodes, CANH1 and CANL1, the receiver output node R1 experiences a change of state from low to high when it should remain low, then transceiver 30 has failed the common-mode rejection test. If, however, during application of the differential applied voltage, the receiver output node R1 remains low or does not experience a change of state, then transceiver 30 has passed the common-mode rejection test. Failure of the common-mode rejection test stems from the difference between the RC time constant of differential output nodes, CANH and CANL.
Conforming with ISO11898 requirements, FIG. 6 illustrates another approach to eliminate the capacitive imbalance in a transceiver architecture. As shown, driver 102 includes outputs, 104 and 106, couples to nodes, CANH2 and CANL2, respectively. Circuits 114 and 120 serve as active devices for transceiver 100. Circuit 114 includes transistor 122 having a gate coupled to power supply VCC, a drain coupled to the gate of transistor 124 and a source coupled to node CANH2. Transistor 124 includes a drain coupled to the power supply VCC and a source couple to node CANH2. Schottky diode 126 couples between power supply VCC and bulk nodes of transistors, 122 and 124. Circuit 120 includes transistor 140 having a gate coupled to power supply VCC, a drain coupled to a Schottky diode 138, a source coupled to ground and a bulk coupled to the source. Schottky diode 138 couples between node CANL2 and the drain of transistor 140. Redundancy through circuits, 116 and 118, is incorporated within this design to correct any capacitive imbalance, such that circuit 116 is a replica of circuit 114 and circuit 118 is a replica of circuit 120.
Dummy devices, 116 and 118, are placed on nodes CANH2 and CANL2 to mimic the capacitance of the active driver on the corresponding node opposite each respective node. Thereby, differential output nodes CANH2 and CANL2 are capacitively balanced. The disadvantage of this architecture is that the dummy devices, 116 and 118, are designed to be as large as the active devices, 114 and 120, to perfectly balance the receiver input capacitance. The capacitance, however, does not need to be perfectly balanced; rather, the RC time constant is formed by external resistors in a receiver common-mode rejection test implementation and the capacitance of nodes, CANH2 and CANL2, must be balanced.
Furthermore, in order to remain price competitive, minimization of the CAN transceiver die size is an important design criteria. Removing dummy devices, 116 and 118, from the CAN transceiver architecture would suffice to lower die area and would not result in any performance drawbacks; however, it will cause transceiver 100 to fail common-mode rejection test.
Therefore, a need exists for a CAN transceiver that provides improved impedance matching between differential output signals, CANH and CANL, while the requirements of die area are decreased. The impedance matching circuit portions must connect to differential output nodes, CANH and CANL, and capacitively balanced differential output nodes, CANH and CANL, such that the RC time constants formed with external test resistors are equivalent. As a result, the improved transceiver must provide superior common-mode rejection, passing the aforementioned common-mode rejection test.